1. Field of the Invention
This invention relates to a semiconductor device, and in more particularly to the construction of an emitter terminal or electrode of a bipolar transistor.
2. Description of the Prior Art
The fabrication process of a prior semiconductor device is explained with reference to the drawings.
FIG. 1A to 1D show a sectional view of a semiconductor chip showing the sequence of processes in order to explain the fabrication process of a prior semiconductor device.
As shown in FIG. 1A, arsenic ions are selectively implanted into the main surface of a P-type single crystal silicon substrate 1 using an acceleration energy of 70 keV and a dose of 3.times.10.sup.15 to 1.times.10.sup.16 cm.sup.-2, and an N-type buried diffusion layer 2 is formed by performing heat treatment at a temperature of 1050.degree. to 1150.degree. C. for four hours. In the same way, boron ions are selectively implanted using an accelaration energy of 50 keV and a dose of 5.times.10.sup.13 to 3.times.10.sup.14 cm.sup.-2, and a P-type buried diffusion layer 3 is formed by performing heat treatment at a temperature of 980.degree. to 1050.degree. C. for one hour.
Next, an N-type epitaxial layer 4 with a specific resistance of 1.OMEGA. cm is formed with a thickness of 1.5 to 2.5 .mu.m on top of the P-type single crystal silicon substrate 1 which includes the N-type buried diffusion layer 2 and the P-type buried diffusion layer 3, and a P-type diffusion layer 5 is selectively formed extending from the main surface of the N-type epitaxial layer 4 to the P-type buried diffusion layer 3, insulating and isolating the elements. Then, a silicon oxide layer (field oxide film) 6 is formed with a thickness of 600 to 900 nm, using a selective oxidation method, on the surface of the N-type epitaxial layer 4, insulating and isolating the elements, and partitioning off both a first element formation region 7 and a second element formation region 8. Next, a 10 to 20 nm thick silicon oxide layer 9 is formed on the surface of the N-type epitaxial layer 4 of both the first and second element formation regions 7 and 8 using thermal oxidation at a temperature of 900.degree. C. and in an H.sub.2 -O.sub.2 atmosphere. Then, after the silicon oxide layer 9 of the first element formation region 7 has been selectively removed, a 250 to 450 nm thick polycrystalline silicon layer 10 with phosphorus doped is selectively formed and will act as a collector electrode. For example, in a semiconductor device with bipolar elements and MOS elements configured on the same semiconductor substrate, the silicon oxide layer 9 is formed using the same process as a gate oxide film, and the polycrystalline silicon layer 10 is formed simultaneously with the gate electrode. Doping of phosphorus into the polycrystalline silicon layer 10 is performed using diffusion at 830.degree. to 930.degree. C., also at the same time, phosphorus is diffused into the N-type epitaxial layer 4 passing through the polycrystalline silicon layer 10 forming an N-type collector diffusion layer 11. Next, using an acceleration energy of 10 to 30 keV and a dose of 1.times.10.sup.13 to 5.times.10.sup.13 cm.sup.-2, boron ions are implanted into the surface of the N-type epitaxial layer 4 of the second element formation region 8 to form a P-type intrinsic base diffusion layer 12, and boron ions are selectively implanted into a portion of the P-type intrinsic base diffusion layer 12 using an acceleration energy of 10 to 30 keV and a dose of 3.times.10.sup.15 to 1.times.10.sup.16 cm.sup.-2 to form a P-type base extrinsic diffusion layer 13.
Next, as shown in FIG. 1B, a 250 nm thick silicon oxide layer 14 is deposited on all surfaces using a CVD (chemical vapor deposition) method, and an open-hole region is selectively prepared in the silicon oxide layer 14 above top of the P-type intrinsic base diffusion layer 12, and in the open-hole region, a 200 nm polycrystalline silicon layer 15 with arsenic doped is selectively formed as an emitter electrode. Arsenic is doped into the polycrystalline silicon layer 15 by implanting arsenic ions using an acceleration energy of 70 keV and a dose of 5.times.10.sup.15 to 2.times.10.sup.16 cm.sup.-2, and then by forcing the arsenic using heat treatment at 900.degree. to 950.degree. C. an N-type emitter diffusion layer 16 is formed inside the P-type intrinsic base diffusion layer 12.
As shown in FIG. 1C, an interlayer insulating film 17 comprised of two layers is prepared by depositing in succession using the CVD method, a 100 nm thick silicon oxide layer and a 500 nm thick BPSG layer on top of the silicon oxide layer 14 including the polycrystalline silicon layer 15, and then in order to smooth the surface, heat treatment is performed at 850.degree. to 920.degree. C. after which holes are selectively opened in the interlayer insulating film 17 and open-hole regions 18, 19, and 20 are selectively formed extending to the collector terminal or electrode 10, emitter terminal or electrode 15 and the P-type base extrinsic diffusion layer 13.
Next, as shown in FIG. 1D, an aluminum layer is deposited on the surfaces which contain the open-hole regions 18, 19, and 20, it is then patterned and the wirings 21 connecting the collector electrode 10, the emitter electrode 15 and the P-type base extrinsic diffusion layer 13 are formed interconnecting the elements in the semiconductor device.
In the prior semiconductor device, the surface of the interlayer insulating film 17 needed to be flattened sufficiently in order to prevent shorts and breaks in the wiring layers 21 which are formed in a later process. The vertical distances from the surface of the interlayer insulating film 17 to the collector electrode 10, the emitter electrode 15 and the P-type base extrinsic diffusion layer 13 are 850 nm, 600 nm and 850 nm respectively at the time the interlayer insulating film 17 is deposited. However, after heat treatment, they change to approximately 900 nm, 500 nm and 950 nm. If the open-hole regions 18, 19 and 20 are formed by, for example, plasma etching using a CHF.sub.3 --O.sub.2 family gas, it is necessary to set etching conditions which match the film thickness of the silicon oxide layers on top of the P-type base extrinsic diffusion layer 13. When the etching ratio for the ply crystalline silicon layers 10 and 15 and silicon oxide layers 6 and 14 using the gas family mentioned above is 1:6, the emitter electrode 15 is etched and removed by at least 80 nm [(950-500)/6=75 nm] thick during plasma etching. Under the above conditions, the thickness of the emitter electrode 15 is actually reduced from 200 nm to 120 nm. This differs depending on how large or small the heat history is after the aluminum wiring 21 is formed in a later process, however, in order that there are no changes in the bipolar transistor characteristics due to the reaction of the aluminum wiring layer 21 with the polycrystalline silicon of the emitter electrode 15, it is necessary that the film thickness of the emitter electrode 15 be 70 to 100 nm after the open-hole region 19 is formed. Therefore, a film thickness for the emitter electrode 15 of 180 nm or more, or if the irregularities occurring during fabricating are considered, a thickness of 200 nm or more is desirable.
On the other hand, in order to make high-integration and high-performance of the elements possible, the open-hole region (emitter contact hole) formed on the silicon oxide layer 14 is gradually reduced. For example, for a 250 nm thick silicon oxide layer 14, a width of 700 nm and a length of 3 .mu.m are applicable dimensions. In order to reduce the irregularities in the element characteristics of the bipolar transistor, it is necessary that the thickness of the polycrystalline silicon layer 15 is the same as that of the silicon oxide layer 14, and in order to reduce the irregularities of the quantity of arsenic ions implanted into the emitter electrode 15 in a later process, it is necessary that the width of the selected open-hole be three times or more the thickness of the emitter electrode 15. Thus, it is necessary that the thickness of the emitter electrode 15 be 230 nm or less.
In the prior semiconductor device described above, irregularities in the characteristics of the bipolar transistor are large due to irregularities during fabricating. Also, there is a problem in that product yield drops easily.
Also, in order to make the width of the emitter contact holes even smaller, a problem exists in that the reduction in the width cannot be dealt with expansion of the prior fabricating technology, i.e. with only a reduction in the dimensions in the vertical and horizontal directions.